Daewoo DTR Series Especificações descarregar pdf (Página 13)

• Micro

controller

- 8 bit C500-CPU (8051 compatible)

- 18 MHz internal clock

- 0.33 µs instruction cycle

- Eight 16-bit data pointer registers (DPTR)

- Two 16-bit timers

- Watchdog timer

- Capture comprare timer for infrared remote control decoding

- Serial interface (UART)

- 256 bytes on-chip RAM

- 8 Kbyte on-chip on-chip display-RAM (access via MOVX) for SDA 5250, SDA 5254 and SDA 5252

- 1 Kbyte on-chip display-RAM (access via MOVX) for SDA 5250, SDA 5254 and SDA 5255

- 1 Kbyte on-chip TVT/VPS-Acquisition-buffer-RAM (access via MOVX)

- 1 Kbyte on-chip extended-RAM (access via MOVX) for SDA 5250, SDA 5254 and SDA 5255

- 6 channel 8-bit pulse width modulation unit

- 2 channel 14-bit pulse width modulation unit

- 4 multiplexed ADC inputs with 8-bit resolution

- One 8-bit I/O port with open drain output and optional I

C-Bus emulation (PORT 0)

- Two 8-bit multifunctional I/O ports (PORT 1, PORT3)

- One 4-bit port working as digital or analog inputs (PORT 2)

- One 2-bit I/O port with optional function

- One 3-bit I/O port with optional RAM/ROM address expansion up to 512 Kbyte (ROMIess-Version)

•

P-SDIP-52-1 package or P-MQFP-64-1 for ROM-Versions (SDA 5251, SDA 5252, SDA 5254, SDA 5255)

•

P-MQFP-80-1 Package for ROMIess-Version (SDA 5250 M)

•

P-LCC-84-2 Package for Emulator-Version (SDA 5250)

•

5 V Supply Voltage

(3) Block Diagram

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 72 73

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Daewoo DTR Series Especificações Página 13